ADSP-214xx SHARC Processor Hardware Reference 16-11
Peripheral Timers
To control the assertion sense of the
TIMERx_O signal, the PULSE bit in the
corresponding TMxCTL register is either cleared (causes a low assertion
level) or set (causes a high assertion level).
When enabled, a timer interrupt is generated at the end of each period. An
ISR must clear the interrupt latch bit TIMxIRQ and might alter period
and/or width values. In pulse width modulation applications, the program
can update the period and pulse width values while the timer is running.
When a program updates the timer configuration, the TMxW register
must always be written to last, even if it is necessary to update only
one of the registers. When the TMxW value is not subject to change,
the ISR reads the current value of the TMxW register and rewrite it
again. On the next counter reload, all of the timer control registers
are read by the timer.
To generate the maximum frequency on the TIMERx_O output signal, set
the period value to two and the pulse width to one. This makes the TIMERx
signal toggle every 2 PCLK clock cycles as shown in Figure 16-9. Assuming
PCLK = 133 MHz:
Maximum period = 2 × (2
31
– 1) × 7.5 ns = 32 seconds.
If your application requires a more sophisticated PWM output
generator, refer to Chapter 7, Pulse Width Modulation.
Single-Pulse Generation
If the
PRDCNT bit is cleared, the PWM_OUT mode generates a single pulse on
the TIMERx_O signal. This mode can also be used to implement a well
defined software delay that is often required by state machines. The pulse
width (= 2 × TMxW) is defined by the width register and the period register
should be set to a value greater than the pulse width register.
At the end of the pulse, the interrupt latch bit (
TIMxIRQ) is set and the
timer is stopped automatically. If the
PULSE bit is set, an active high pulse
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