ADSP-214xx SHARC Processor Hardware Reference 21-19
Two Wire Interface Controller
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
TWI Effect Latency
After the TWI registers are configured the effect latency is 1.5 PCLK cycles
minimum and 2 PCLK cycles maximum.
Programming Model
The following sections include information for general setup, slave mode,
and master mode, as well as guidance for repeated start conditions.
General Setup
General setup refers to register writes that are required for both slave
mode and master mode operation. General setup should be performed
before either the master or slave enable bits are set.
Programs should enable the TWI controller through the
TWIMITR register
and set the prescale value. Program the prescale value to the binary repre-
sentation of f
PCLK
/10 MHz.
All values should be rounded up to the next whole number. The
TWIEN
enable bit must be set. Note that once the TWI controller is enabled, a
bus busy condition may be detected.
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