Peripheral Registers
A-98 ADSP-214xx SHARC Processor Hardware Reference
System Mask Configuration Register (MLB_SMCR)
This register, described in Table A-60, allows system software to mask sys-
tem status interrupts. When a mask bit is set, the corresponding system
channel interrupt is masked.
Table A-59. MLB_SDCR Register Description (RO)
Bit Name Description
31–0 SDATA System Channel Data.
Figure A-47. MLB_SMCR Register
Table A-60. MLB_SMCR Register Bit Descriptions (RW)
Bit Name Description
0SMRSystem Masks Reset Command. When set, this bit masks system inter-
rupts for Mlb Reset system command.
2SMNUSystem Masks Network Unlock. When set, this bit masks system inter-
rupts for the MOST_unlock system command.
1SMNLSystem Masks Network Lock. When set, this bit masks system interrupts
for the MOST_Lock system command.
3SMCSSystem Masks Channel Scan. When set, this bit masks system interrupts
for MlbScan system command.
SMNU
SMNL
SMCS
SMML
SMR
System Masks Reset Command
System Masks MLB Unlock
SMSC
System Masks Subcommand
System Masks MLB Lock
SMMU
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
System Masks Network Unlock
System Masks Network Lock
System Masks Channel Scan
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