Operating Modes
2-34 ADSP-214xx SHARC Processor Hardware Reference
Listing 2-1. Chain Assignment
R0=0;
dm(CPx)=R0; /* clear CPx register */
/* init DMA control registers */
R2=(TCB1+3) & 0x7FFFF; /* load IIx address of next TCB
and mask address */
R2=bset R2 by 19; /* set PCI bit */
dm(TCB2)=R2; /* write address to CPx location of
current TCB */
R2=(TCB2+3) & 0x7FFFF; /* load IIx address of next TCB and
mask address*/
R2=bclr R2 by 19; /* clear PCI bit */
dm(TCB1)=R2; /* write address to CPx location of
current TCB */
dm(CPx)=R2; /* write IIx address of TCB1 to CPx
register to start chaining*/
Chained DMA operations may only occur within the same chan-
nel. The processor does not support cross-channel chaining.
Starting Chain Loading
A DMA sequence is defined as the sum of the DMA transfers for a single
channel, from when the parameter registers initialize to when the count
register decrements to zero. Each DMA channel has a chaining enable bit
(CHEN) in the corresponding control register.
To start the chain, write the internal index address of the first TCB to the
chain pointer register. When chaining is enabled, DMA transfers are initi-
ated by writing a memory address to the chain pointer register. This is also
an easy way to start a single DMA sequence, with no subsequent chained
DMAs.
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