Data Transfer Types
20-12 ADSP-214xx SHARC Processor Hardware Reference
length of a single word. A receive filter removes spurious pulses of less
than two times the sampling clock period.
Because of the destructive nature of reading this register, a shadow
register is provided for reading the contents of the corresponding
main register. For more information, see “Debug Features” on
page 20-20.
Core Transfers
Core transfers move data to and from the UART by the processor core. To
transmit a character, load it into the UARTTHR register. Received data can
be read from the UARTRBR register. The processor must write and read one
character at time.
To prevent any loss of data and misalignments of the serial data stream,
the UART line status register (
UARTLSR) provides two status flags for hand-
shaking—
UARTTHRE and UARTDR.
The
UARTTHRE flag is set when the UARTTHR register is ready for new data
and cleared when the processor loads new data into the UARTTHR register.
Writing this register when it is not empty overwrites the register with the
new value and the previous character is never transmitted.
The UARTDR flag signals when new data is available in the UARTRBR register.
This flag is cleared automatically when the processor reads from this
Figure 20-4. UART Receive Buffer Register
Higher Byte (23–16)
Lower Byte (7–0)
RX9D0
RX9D1
Zero-Filled
Zero-Filled
09 837564 2114 12 11 101315
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
To Next Page
Loading...
Need help?
General
