Interrupts
15-24 ADSP-214xx SHARC Processor Hardware Reference
Full Duplex Operation
The SPI interface allows full-duplex operation running the DMA channel
to the transmit/receive path and core access to the alternate trans-
mit/receive path. For full-duplex operation, set
TIMOD = 10 which
generates the interrupts for DMA only.
Reads from the RXSPIx buffer are allowed at any time during transmit
DMA. Note the TXS bit is cleared when the TXSPIx buffer is read but the
DMA FIFO is not available in the receive path. The receive interface can-
not generate an interrupt, but the RXS status bits can be polled.
Writes to the TXSPIx buffer during an active SPI receive DMA operation
are permitted. Note the RXS bit is cleared when the RXSPIx buffer is read
but the DMA FIFO is not available in the transmit path. The transmit
interface cannot generate an interrupt, but the TXS status bits can be
polled.
Interrupts
The following section describes SPI operations using both the core and
direct memory access (DMA). Table 15-7 provides an overview of SPI
interrupts.
Interrupt Sources
The SPI ports can generate interrupts in five different situations. During
core-driven transfers, an SPI interrupt is triggered:
1. When the
TXSPI buffer has the capacity to accept another word
from the core.
2. When the RXSPI buffer contains a valid word to be retrieved by the
core.
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