SDRAM Controller (ADSP-2147x/ADSP-2148x)
3-26 ADSP-214xx SHARC Processor Hardware Reference
Address Translation Options
To provide flexible addressing, the SDADDRMODE bit (bit 31) in the SDCTL0
register is used to select the address mapping scheme—page interleaving
or bank interleaving (default).
Page Interleaving Map
Programming the SDADDRMODE bit to 1 selects the page interleaving scheme.
In this scheme consecutive pages fall in consecutive banks. The bank
address bits follow the most significant column address bits. This is shown
in Figure 3-7.
One advantage of the page interleaving is that the effective page size is up
to four pages (assuming four banks activated) and all the addresses are
sequential. If using delay line DMA mode, the addresses for a long delay
line are all sequential, simplifying the addressing. Moreover, SDRAM
sequential addressing provides maximum performance.
Page interleaving is not supported with 2 bank devices.
Bank Interleaving Map
Programming the SDADDRMODE bit to 0 selects the bank interleaving
scheme. In this scheme consecutive pages sit in the same bank. The bank
address bits follow the most significant row address bits. This is shown in
Figure 3-7.
One advantage of bank interleaving is that the effective page size is also up
to four pages (assuming that four banks are activated) but the addresses of
the four pages are not sequential. If using two external port DMAs point-
ing to the SDRAM space, this scheme has the advantage where every bank
uses single DMA buffer addressing.
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