SDRAM Controller (ADSP-2147x/ADSP-2148x)
3-32 ADSP-214xx SHARC Processor Hardware Reference
Table 3-10 where
SDADDRMODE = 0, X16DE = 1, SDRAW2–0 = 100 (12 bits),
and SDCAW1–0 = 11 (11 bits).
Refresh Rate Control
The SDRAM refresh rate control register provides a flexible mechanism
for specifying auto-refresh timing. The SDC provides a programmable
refresh counter which has a period based on the value programmed into
the lower 12 bits of this register. This coordinates the supplied clock rate
with the SDRAM device’s required refresh rate.
Table 3-10. Page Interleaving Map (2K Page Size)
Pin Column Address Row Address Bank Address Pins of SDRAM
A[18] IA[22] BA[1]
A[17] IA[21] BA[0]
A[13]
A[12] A[12]
A[11] IA[20] A[11]
SDA10 IA[19] A[10]
A[9] IA[8] IA[18] A[9]
A[8] IA[7] IA[17] A[8]
A[7] IA[6] IA[16] A[7]
A[6] IA[5] IA[15] A[6]
A[5] IA[4] IA[14] A[5]
A[4] IA[3] IA[13] A[4]
A[3] IA[2] IA[12] A[3]
A[2] IA[1] IA[11] A[2]
A[1] IA[0] IA[10] A[1]
A[0] 1/0 IA[9] A[0]
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