Features
15-2 ADSP-214xx SHARC Processor Hardware Reference
Features
The processor’s SPI ports provide the following features and capabilities.
• A simple 4-wire interface consisting of two data pins, a device
select pin, and a clock pin.
• Special data formats to accommodate little and big endian data,
different word lengths, and packing modes.
• Master and multiples slave (multi devices) in which the
ADSP-214xx master processor can be connected to up to four
other SPI devices.
• Parallel core and DMA access allow full duplex operation.
• Open drain outputs to avoid data contention and to support
multimaster scenarios.
Transmission Full Duplex Yes (Core and DMA)
Access Type
Data Buffer Yes
Core Data Access Yes
DMA Data Access Yes
DMA Channels 1
DMA Chaining Yes
Interrupt Source Core/DMA
Boot Capable Yes
Local Memory No
Clock Operation f
PCLK
/4 (slave) f
PCLK
/8 (master)
Table 15-1. SPI Port Specifications (Cont’d)
Feature SPI/SPIB
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