Operation Modes
10-36 ADSP-214xx SHARC Processor Hardware Reference
field is a read-only status indicator. The
CHNL(6:0) bits increment modulo
NCH(6:0) as each channel is serviced.
Active Channel Selection Registers
Specific channels can be individually enabled or disabled to select the
words that are received and transmitted during multichannel communica-
tions. Data words from the enabled channels are received or transmitted,
while disabled channel words are ignored. Up to 128 channels are avail-
able for transmitting and receiving.
The multichannel selection registers enable and disable individual chan-
nels. The registers for each serial port are shown in“Serial Port Registers”
on page A-150.
Each of the four multichannel enable and compand select registers are 32
bits in length. These registers provide channel selection for 128 (32 bits x
4 channels = 128) channels. Setting a bit enables that channel so that the
serial port selects its word from the multiple-word block of data (for either
receive or transmit). For example, setting bit 0 for TX SPORT0 and TX
SPORT7 (MT0CS0 or MT7CS0) selects channel 0, setting bit 12 selects chan-
nel 12, and so on. Setting bit 0 for TX SPORT0 and TX SPORT7
(MT0CS1 or MT7CS1) selects channel 32, setting bit 12 selects channel 44,
and so on.
Companding Selection
Companding may be selected on a per-channel basis. Setting a bit to 1 in
any of the multichannel registers (MTxCCSy or MRxCCSy) specifies that the
data be companded for that channel. A-law or μ-law companding can be
selected using the
DTYPE bit in the SPCTLx control registers. SPORTA1, 3,
5 and 7 expand selected incoming time slot data, while SPORTA0, 2, 4
and 6 can compress the data.
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