FIR Accelerator
6-42 ADSP-214xx SHARC Processor Hardware Reference
Floating-Point Data Format
The FIR accelerator treats data and coefficients in 32-bit floating-point
format as the default functional mode.
Fixed-Point Data Format
In fixed-point mode, the 32-bit input data/coefficient is treated as
fixed-point. A 32-bit fixed-point MAC operation generates an 80-bit
result. Fixed-point data/coefficients can be unsigned integer, unsigned
fractional and signed integer.
In fixed point mode, the entire 80-bit result register is always writ-
ten back in bursts of 3 × 32 bits. The first word is the LSW, the
2nd the MSW and the third word is a 16-bit overflow, the remain-
ing 16-bits are padded with zeros. Therefore for fixed-point
WINDOWSIZE = WINDOWSIZE × 3.
If signed fractional format is used, the output needs to be scaled by
2 since the MAC does not the right shift to remove the redundant
sign bit. A final routine needs to decimate the output buffer to the
desired samples.
Multi iteration mode is not supported in this format. Therefore, the max-
imum TAP length is 1024.
Data Transfer
The FIR filter works exclusively through DMA.
DMA Access
The FIR accelerator has two DMA channels (accelerator input and out-
put) to connect to the internal memory. The DMA controller fetches the
data and coefficients from memory and stores the result.
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