Clocking
11-6 ADSP-214xx SHARC Processor Hardware Reference
IDP Control Registers (IDP_CTLx). The ADSP-2136x and
ADSP-2137x SHARC processors have two IDP control registers. The
IDP_CTL1-0 registers are used to control the SIP operations.
PDAP Control Register (IDP_PP_CTL). The register (shown in
Figure 11-1) is used to control all PDAP operations.
IDP Status Register (IDP_STAT). The register returns different types of
status for SIP/PDAP core and DMA operations.
Clocking
The fundamental timing clock of the IDP module is peripheral clock/4
(PCLK/4). The IDP SIP/PDAP operates in slave mode only.
Functional Description
The IDP provides up to eight serial input channels—each with its own
clock, frame sync, and data inputs. The eight channels are automatically
multiplexed into a single 32-bit by eight-deep FIFO. Data is always for-
matted as a 64-bit frame and divided into two 32-bit words. The serial
protocol is designed to receive audio channels in I
2
S, left-justified, or
right-justified mode. One frame sync cycle indicates one 64-bit left-right
pair, but data is sent to the FIFO as 32-bit words (that is, one-half of a
frame at a time). Transfers from this FIFO to internal memory can be per-
formed either via DMA or by interrupts driven by the core.
IDP Channel 0 is shared by SIP0 and PDAP. All other 7 SIPs are
connected to corresponding IDP channel of FIFO.
The DMA engine of the IDP implements DMA for all the 8 channels. It
has eight sets of DMA parameter registers for 8 channels. Data from chan-
nel 0 is directed to internal memory location controlled by set of registers
for channel 0 and so on.
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