ADSP-214xx SHARC Processor Hardware Reference 3-59
External Port
meeting the required timing specifications, pulls down the
DDR2CKE signal.
If an internal access is pending, the controller delays entering the
power-down mode until it completes the pending DDR2 access and any
subsequent pending access requests.
• DIS_DDR2CKE = 0 No effect.
• DIS_DDR2CKE = 1 Enter precharge power down.
Once the DDR device enters into power-down mode, the DDR controller
asserts the DDR2PD bit in the DDR control status register (DDR2STAT0).
Unlike self-refresh mode, precharge power-down entry mode does
not refresh the DDR2 device. Therefore, careful software control is
required so as not to violate refresh conditions which leads to data
corruption. The typical refresh interval of t
REFI
can be extended up
to 8 × t
REFI
. Consult the DDR2 data sheet for complete
information.
This mode is useful if the DDR2 operation is idling only for a short period
of time. This time is limited by the JEDEC spec and is typically 9 × t
REFI
.
If for example t
REFI
= 7.8µs the maximum power-down time is 9 × 7.8µs =
70µs.
When DDR2 memory pauses for a short period of time, systems should
evaluate on a case by case basis whether or not self-refresh or precharge
power-down should be used. This consideration will take into account
that precharge power-down is limited to a timing window of approxi-
mately 70 µs (9 × t
REFI
), and that self-refresh release requires 200 DDR2
cycles for the DLL to lock again.
Precharge Power-down Exit
The DDR2 device exits power-down mode only when the DIS_DDRCKE bit
in the control register is cleared. The controller takes care of the
power-down exit timing specifications t
XP
, t
XARD
, t
XARDS
and t
CKE
min.
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