ADSP-214xx SHARC Processor Hardware Reference 6-29
FFT/FIR/IIR Hardware Modules
Register Overview
The FIR accelerator registers are described below.
Power Management Control Register (PMCTL1). Used for FIR acceler-
ator selection. Controls the clock power down to the module if not
required.
Control Registers (FIRCTLx). Used to configure the global parameters
for the accelerator. These include the number of channels, channel auto
iterate, DMA enable, and accelerator enable.
The FIRCTL2 register is used to configure the channel specific parameters
such as filter TAP length, window size, sample rate conversion, up/down
sampling and ratio.
DMA Status Register (FIRDMASTAT). Provides the status of the FIR
accelerator operation. This information includes chain pointer loading,
coefficient DMA, data preload DMA, processing in progress, window pro-
cessing complete, and all channels processing complete.
MAC Status Register (FIRMACSTAT). Provides the status of MAC oper-
ation for all four multiply accumulators. In fixed-point mode, only the
ARIx (adder result infinity) is used, all other bits are reserved.
Debug Control Register (FIRDEBUGCTL). Controls the debug mode
operation of the accelerator.
Clocking
The FIR accelerator runs at the maximum speed of the peripheral clock
frequency (f
PCLK
).
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