ADSP-214xx SHARC Processor Hardware Reference 2-15
I/O Processor
UART TCB
The UART interface supports both single and chained DMA. However,
unlike the serial ports, programs cannot insert a TCB in an active chain.
Table 2-16 shows the required TCBs for chained DMA.
Link Port TCB
The link port interface supports both single and chained DMA.
Table 2-17 shows the required TCBs for chained DMA.
Table 2-16. UART0 TCBs
Address Register
CP[18:0] RXCP_UAC0/TXCP_UAC0 Chain Pointer
CP[18:0] + 0x1 RXC_UAC0/TXC_UAC0 Internal Count
CP[18:0] + 0x2 RXM_UAC0/TXM_UAC0 Internal Modifier
CP[18:0] + 0x3 RXI_UAC0/TXI_UAC0 Internal Index
Table 2-17. Link Port TCBs
Address Register
CP[18:0] CPLPx Chain Pointer
CP[18:0] + 0x1 CLBx Internal Count
CP[18:0] + 0x2 IMLBx Internal Modifier
CP[18:0] + 0x3 IILBx Internal Index
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