DDR2 DRAM Controller (ADSP-2146x)
3-52 ADSP-214xx SHARC Processor Hardware Reference
• Bits 6–4 – CAS latency, programmable in the
DDR2CTL0 register
• Bit 7 – Always 0
• Bit 8 – reset DLL (DDR2 device)
• Bits 11–9 = Reserved
• Bits 13–12 = Always zero
• Bits 15–14 (00 – selects mode register)
While executing this command, the unused address pins are set to zero.
During the first DDR2_CLK cycle following the command, the controller
issues a NOP command. This command can also be triggered by setting the
FLMR bit in the DDR2CTL0 register.
To automatically start the power-up sequence, (no dummy access
are required) set the DDR2PSS bit (=1).
Load Extended Mode Register
This command initializes DDR2 operation parameters (other than those
controlled by mode register). This command is a part of the power-up
sequence, initiated by writing 1 to the DDR2PSS bit in the DDR2 memory
control register (DDR2CTL0). This command uses the address bus of the
controller for data input.
Values written into DDR2CTL3 register are loaded into the EMR register dur-
ing power up. The command initializes the following parameters:
1. Bit 0 – DLL enable/disable
2. Bit 1 – ODS (output drive strength—reduced/full)
3. Bits 2, 6 = Rtt value (ODT feature)
4. Bits 5–3 = Additive latency from 0 to 5
5. Bits 9–7 = Always zero
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