ADSP-214xx SHARC Processor Hardware Reference A-9
Registers Reference
Power Management Control Register 1
(PMCTL1)
This register, shown in Figure A-3 and described in Table A-4, contains
the bits for shutting down the clocks to various peripherals and selecting
one of the three FIR/IIR/FFT accelerators.
Write to this register has effect latency of two PCLK cycles.
17–16 (RO) CRAT PLL Configuration Ratio, CLK_CFG1-0 pins. After reset,
both CLK_CFG pins define the CLKIN to core clock ratio.
This ratio can be changed with the PLLM and PLLD bits.
CRAT =CLK_CFG[1:0]
0 = CLK_CFG[1:0] = 00 (6:1 ratio)
1 = CLK_CFG[1:0] = 01 (32:1 ratio)
2 = CLK_CFG[1:0] = 10 (16:1 ratio)
3 = reserved
20–18 DDR2CKR DDR2CLK Ratio. Core clock to DDR2 clock. Note that the
typical minimum clock speed to typically 125 MHz.
000 = RATIO = 2
010 = RATIO = 3
100, 101, 110, 111 = reserved
22–21 LCLKR Link Port Clock Ratio.
00 = RATIO = 2.0
01 = RATIO = 2.5
10 = RATIO = 3.0
11 = RATIO = 4.0
Reset value = 10
32–23 Reserved
Table A-3. PMCTL Register Bit Descriptions (RW) (Cont’d)
Bit Name Description
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