ADSP-214xx SHARC Processor Hardware Reference 20-5
UART Port Controller
The 16-bit divisor formed by the UARTDLH and UARTDLL registers
resets to 0x0001, resulting in the highest possible clock frequency
by default. If the UART is not used, disabling the UART clock
saves power (see bits 13 and 14 in the “System and Power Manage-
ment Registers” on page A-4). The UARTDLH and UARTDLL registers
can be programmed by software before or after turning on the
clock.
Table 20-3 provides example divide factors required to support most stan-
dard baud rates.
Careful selection of PCLK frequencies, that is, even multiples of
desired baud rates, can result in lower error percentages.
Functional Description
The UART supports multiprocessor communication using 9-bit address
detection. This allows the units to be used in multi-drop networks using
Table 20-3. UART Baud Rate Examples With 100 MHz PCLK
Baud Rate Divisor Latch
(DL)
Actual % Error
2400 2604 2400.15 0.006
4800 1302 4800.31 0.007
9600 651 9600.61 0.006
19200 326 19,171.78 0.147
38400 163 38,343.56 0.147
57600 109 57,339.45 0.452
115200 54 115,740.74 0.469
921,600 7 892,857.14 3.119
6,250,000 1 6,250,000 –