FFT Accelerator
6-22 ADSP-214xx SHARC Processor Hardware Reference
LOG2HDIM = 0
FFT_RPT = 0
FFT_CPACKIN/FFT_CPACKOUT = 0 or 1 depending on whether
input/output data is packed into complex words or sent/received
data is real or imaginary.
3. Set (=1) the FFT_RST bit in the FFTCTL1 register and wait for a min-
imum of 4 CCLK cycles.
4. Program control register FFTCTL1 with:
FFT_RST = 0
FFT_EN = 1
FFT_START = 1
FFT_DMAEN = 1
FFT_DEBUG = 0
5. Configure a coefficient DMA to read N complex twiddle factors
from the coefficient buffer into the accelerator (total of 2N 32- bit
words) and wait until the DMA is complete (or chain DMA in Step
4). This step is not needed if twiddles are already in the coefficient
memory of the accelerator.
6. Configure a data DMA to read N complex data points from the
input buffer into the accelerator (total of 2N 32-bit words).
7. Configure a data DMA to write N complex data points from the
accelerator into the output buffer (total of 2N 32-bit words). There
is no need to wait until the DMA in Step 6 completes.
8. Wait until the DMA in Step 7 completes (by interrupt or polling).
The computed FFT is now in the core’s internal memory and the
accelerator is in idle mode.
N <= 256, Repeat
For details on the storage format of the coefficients see “Internal Memory
Storage” on page 6-8 .
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