ADSP-214xx SHARC Processor Hardware Reference 6-23
FFT/FIR/IIR Hardware Modules
1. Configure the
ACCSEL bits in the PMCTL1 register to select the FFT
accelerator.
2. Program the FFTCTL2 register with:
VDIM = N/16
LOG2VDIM = Log2(N)
HDIM = 0
LOG2HDIM = 0
FFT_RPT = 1
FFT_CPACKIN/FFT_CPACKOUT = 0 or 1 depending on whether
input/output data is packed into complex words or sent/received
data is real or imaginary.
3. Set (=1) the FFT_RST bit in the FFTCTL1 register and wait for a min-
imum of 4 CCLK cycles.
4. Program the FFTCTL1 register with:
FFT_RST = 0
FFT_EN = 1
FFT_START = 1
FFT_DMAEN = 1
FFT_DEBUG = 0
5. Configure a coefficient DMA to read N complex twiddle factors
from the coefficient buffer into the accelerator (total of 2N 32- bit
words) and wait until the DMA is complete (or chain DMA in Step
4). This step is not needed if twiddles are already in the coefficient
memory of the accelerator.
6. Configure a data DMA to read N complex data points from the
input buffer into the accelerator (total of 2N 32-bit words).
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