ADSP-214xx SHARC Processor Hardware Reference 6-5
FFT/FIR/IIR Hardware Modules
Control Register (FFTCTL2). Used to configure individual FFT parame-
ters (such as length) and how the module process the FFT, such as data
packing.
MAC Status Register (FFTMACSTAT). Reports errors and status on the
multiply/accumulator.
DMA Status, Shadow DMA Status Registers (FFTDMASTAT,
FFTSHDMASTAT). Provide information on DMA operations such as
DMA progress and chain pointer loading.
Clocking
The FFT accelerator runs at the maximum speed of the peripheral clock
(f
PCLK
).
Functional Description
The FFT accelerator is comprised of a compute block, data memory and
coefficient memory. The design allows programs to offload an FFT calcu-
lation by initializing few TCBs and control registers. In this way, the FFT
accelerator can perform the FFT calculation in the background while the
core is busy doing some other useful task. It can interrupt the core once
the processing is complete. The following sections provide functional
details of the FFT accelerator.
Compute Block
The compute block contains one complex butterfly stage (based on four
IEEE floating-point multipliers and six IEEE floating-point adders) whose
operation is pipelined and simultaneous.
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