Functional Description
10-20 ADSP-214xx SHARC Processor Hardware Reference
Logic Level Frame Syncs
Frame sync signals may be active high or active low (for example,
inverted). The LFS/LMFS bit in the SPCTLx registers selects the logic level of
the frame sync signals as active low (inverted) if set (=1) or active high if
cleared (=0). Active high (=0) is the default.
Data-Independent Frame Sync
When DIFS = 0 and SPTRAN = 1, the internally-generated transmit frame
sync is only output when a new data word has been loaded into the
SPORT channel’s transmit buffer. Once data is loaded into the transmit
buffer, it is not transmitted until the next frame sync is generated. This
mode of operation allows data to be transmitted only at specific times.
When DIFS = 0 and SPTRAN = 0, a receive SPORTx_FS signal is generated
only when receive data buffer status is not full.
The data-independent frame sync mode allows the continuous generation
of the SPORTx_FS signal, with or without new data in the buffers. The DIFS
bit of the SPCTLx control register configures this option. When DIFS = 1
and SPTRAN = 1, a transmit SPORTx_FS signal is generated regardless of the
transmit data buffer status. When DIFS = 1 and SPTRAN = 0, a receive
SPORTx_FS signal is generated regardless of the receive data buffer status.
Note that the SPORT DMA controller typically keeps the transmit buffer
full. The application is responsible for filling the transmit buffers with
data.
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