ADSP-214xx SHARC Processor Hardware Reference 16-5
Peripheral Timers
During the external event watchdog (EXT_CLK) mode, the period register
is write-only. Therefore, the period buffer is used in this mode to insure
high/low period value coherency.
Pulse Width Register (TMxW). During the pulse width modulation
(PWM_OUT), the width value is written into the timer width registers.
Both width and period register values must be updated “on the fly” since
the period and width (duty cycle) change simultaneously. To insure
period and width value concurrency, a 32-bit period buffer and a 32-bit
width buffer are used.
During the pulse width and period capture (WDTH_CAP) mode, both
the period and width values are captured at the appropriate time. Since
both the width and period registers are read-only in this mode, the exist-
ing 32-bit period and width buffers are used.
When the processor is in EXT_CLK mode, the width register is unused.
Read-Modify-Write
The traditional read-modify-write operation to enable/disable a peripheral
is different for the timers. For more information, see “Peripheral Timer
Registers” on page A-269.
Clocking
The fundamental timing clock of the peripheral timers is peripheral
clock/4 (PCLK/4).
Functional Description
Each timer has one dedicated bidirectional chip signal, TIMERx. The two
timer signals are connected to the 14 digital peripheral interface (DPI)
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