Interrupt Acknowledge
B-2 ADSP-214xx SHARC Processor Hardware Reference
The interrupt regeneration restriction does not apply to any
SPORT in DMA operation mode.
1. Read an IOP register from the same peripheral block before the
return from interrupt (RTI). The read forces the write to occur as
shown in the example codes below.
ISR_SPI_Routine:
R0 = dm(i0,m0);
dm(TXSPI) = R0; /* write to SPI data buffer */
R0 = dm(SPICTL); /* force dummy read to terminate write */
rti;
ISR_PWM_Routine:
r1=PWM_STAT3;
dm(PWMGSTAT)=r1; /* W1C to PWM status reg */
r0=dm(PWMGSTAT); /* force dummy read to terminate write */
rti
;
2. Add sufficient NOP instructions after a write. In the worst case,
programs need to add ten NOP instructions after a write, as shown
in the example code below.
ISR_Routine:
R0 = 0x0;
dm(SPICTL) = R0; /* or disable SPI control */
nop; nop; nop; nop; nop;
nop; nop; nop; nop; nop;
rti;
Interrupt Acknowledge
As previously discussed in this manual, interrupt driven I/O is advanta-
geous in that programs do not need to poll the core. When an interrupt is
triggered, the sequencer typically finishes the current instruction and
jump to the IVT (interrupt vector table). From IVT the address then typ-
ically vectors to the ISR routine. The sequencer jumps into this routine,
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