Debug Features
20-20 ADSP-214xx SHARC Processor Hardware Reference
Debug Features
The following sections describe the debugging features available on the
UART.
Shadow Registers
Because of the destructive nature of reading the following registers: inter-
rupt identification (UARTIIR), line status (UARTLSR) and read buffer
(UARTRBR) shadow registers are provided for reading the contents of the
corresponding main registers. The shadow registers, (UARTIIRSH), (UARTL-
SRSH) and (UARTRBRSH) return exactly the same contents as the main
register, but without changing the register’s status in any way.
Shadow Buffer
Because of the destructive nature of reading the read buffer (UARTxRBR) a
shadow buffer is provided. The shadow buffer (UARTxRBRSH) returns
exactly the same contents as the main buffer, but without changing the
register’s status in any way.
Loop Back Routing
The UART support an internal loop back mode by using the SRU. For
more information, see “Loop Back Routing” on page 9-40.
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
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