ADSP-214xx SHARC Processor Hardware Reference 23-31
System Design
Backward Compatibility
The multiplexing scheme is not backward compatible to previous SHARC
processors. On previous SHARC processors only the external port data
pins are multiplexed. With the ADSP-214xx processors, address and data
pins of the external port are multiplexed.
Parallel Connection of Flag Pins via External Port
and DPI Pins
The various external port multiplexing (shown in Figure 23-10) and DPI
routing options allow situations where the flag direction paths from the
core to the external port or DPI pins operates in parallel. Note that:
For FLAG3–0
• In output mode, if the same flag is mapped to both external port
pins and FLAG3-0 pins, then the output is driven to both pins.
• In input mode, if the same flag is mapped to both external port
pins and FLAG3-0 pins, then the input from external port pins has
priority.
For FLAG15–4
• In output mode, if the same flag is mapped to both external port
pins and DPI pins, then the output is driven from both pins.
• In input mode, if the same flag is mapped to both external port
pins and DPI pins, then the input from the external port pins has
priority.
• In input mode, if the same flags are mapped to both the upper
AMI (
ADDR23-8) and lower AMI (ADDR7-0, DATA7-0) pins, then the
input from lower AMI pins have priority.
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