Index
I-18 ADSP-214xx SHARC Processor Hardware Reference
optimization (continued)
SDRAM reads, example, 3-42
SDRAM reads, external port DMA
example, 3-43
SDRAM throughput, 3-117
OR, logical, 11-32
P
package availability, 1-2
packing
16 to 32-bit packing (PACK) bit, 10-22,
10-45, 10-50, A-154, A-159, A-163
modes in IDP_PP_CTL, illustrated,
11-10
serial peripheral interface (PACKEN)
bit, A-236
packing instructions, 3-90
page size (SDRAM), A-55
parallel data acquisition port control
(IDP_PP_CTL) register, A-179
parallel data acquisition port (PDAP),
11-32
parameter registers, DMA, 2-36
PCG
active low frame sync select for frame
sync (INVFSx) bits, 14-13
bypass mode, 14-13
clock A source (CLKASOURCE) bit,
A-193
clock input (CLKIN) pin, 17-5
clock input source enable
(CLKx_SOURCE_IOP) bit, A-197
clock with external frame sync enable
(FSx_SYNC) bit, A-197
control (PCG_CTL_Ax) registers,
14-13, A-191, A-192
division ratios, 14-18
enable clock (ENCLKx) bit, A-191,
A-192
PCG (continued)
enable frame sync (ENFSx) bit, A-191,
A-192
frame sync A source (FSASOURCE) bit,
14-13, A-193
frame sync B source (FSBSOURCE) bit,
14-13, A-193
frame sync input source enable
(CLKx_SOURCE_IOP) bit, A-197
frame sync with external frame sync
enable (FSx_SYNC) bit, A-197,
A-198
one shot frame sync A or B (STROBEx)
bits, 14-13
one shot option, 14-13
PCG_CTLA0 (control) register, A-191,
A-192
phase shift of frame sync, 14-16
pulse width for frame sync (PWFSx) bit,
A-194
pulse width (PCG_PW) register, 14-13
synchronization with the external clock,
14-20
PCI (program control interrupt) bit, 2-13
PDAP
ena
ble (IDP_PDAP_EN) bit, A-181
port mask bits (IDP_Pxx_PDAPMASK),
A-180
(rising or falling) clock edge
(IDP_PDAP_CLKEDGE) bit, A-181
PDAP control (IDP_PDAP_CTL) register,
A-179
peripheral devices, I/O interface to, 10-1
peripherals
memory mapped, 3-10
peripheral timers
external event watchdog (EXT_CLK)
mode, 16-5, 16-15
input/output (TMRx) pin, 16-5
interrupts, 16-18
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