Peripherals Routed Through the DAI
A-198 ADSP-214xx SHARC Processor Hardware Reference
Figure A-106. PCG_SYNC2 Register
Table A-103. PCG_SYNC2 Register Bit Descriptions (RW)
Bit Name Description
0FSC_SYNC Enable Synchronization of Frame Sync C With External
Frame Sync.
0 = Frame sync disabled
1 = Frame sync enabled
1CLKC_SYNC Enable Synchronization of Clock C With External Frame
Sync.
0 = Clock disabled
1 = Clock enabled
2CLKC_SOURCE_IOPEnable Clock C Input Source.
0 = Output selected by CLKCSOURCE bit
1 = PCLK selected for clock C
3FSC_SOURCE_IOPEnable Frame Sync C Input Source.
0 = Output selected by FSCSOURCE bit
1 = PCLK selected for frame sync C
16 FSD_SYNC Enable Synchronization of Frame Sync D With External
Frame Sync.
0 = Frame sync disabled
1 = Frame sync enabled
Enable Synchronization of
FSD with External LRCLK
FSD_SYNC
FSC_SOURCE_IOP
Enable Frame Sync C Input Source
Enable Synchronization of
FSC with External LRCLK
FSC_SYNC
Enable Synchronization of Clock
C with External LRCLK
CLKC_SYNC
CLKC_SOURCE_IOP
Enable Clock C Input Source
Enable Synchronization of
Clock D with External LRCLK
CLKD_SYNC
FSD_SOURCE_IOP
CLKD_SOURCE_IOP
Enable Clock D Input Source
Enable Frame Sync D Input Source
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
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