Register Overview
8-4 ADSP-214xx SHARC Processor Hardware Reference
Register Overview
The following sections provide brief descriptions of the registers used by
the MediaLB interface. For complete bit descriptions, see “Media Local
Bus Registers” on page A-94.
Device Configuration and Status Registers
These registers are used to set up the basic features of the interface and to
report status of the MLB network. They include the following registers.
• Device Control Configuration Register (MLB_DCCR). Controls
the device enable/disable, clock rate, lock status and addressing of
the MLB.
• System Status Register (MLB_SSCR), System Data Configura-
tion Register (MLB_SDCR), System Mask Configuration
Register (MLB_SMCR). Controls system features of the MediaLB
interface and system interrupt handling.
• Synchronous Base Register (MLB_SBCR), Asynchronous Base
Register (MLB_ABCR), Isynchronous Base Register
(MLB_IBCR). Defines the base address for control RX/TX system
memory buffers.
Channel Configuration Registers
These registers are used to configure and monitor individual MLB chan-
nels. They include the following registers.
• Channel Control Registers (MLB_CECRx). Defines basic attri-
butes about a given logical channel, such as the channel enable,
channel type, channel direction, and channel address. The defini-
tion of the bit fields in this register vary depending on the selected
channel type.
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