ADSP-214xx SHARC Processor Hardware Reference 10-9
Serial Ports
frame sync (
SPORTx_FS) is considered a receive frame sync if the data
signals are configured as receivers. Likewise, the frame sync SPORTx_FS is
considered a transmit frame sync if the data signals are configured as
transmitters. The divisor is a 15-bit value, (bit 0 in divisor register is
reserved) allowing a wide range of serial clock rates. Use the following
equation to calculate the serial clock frequency:
Transmit master: SCLK = PCLK ÷ (4(CLKDIV + 1))
Receive master: SCLK = PCLK ÷ (8(CLKDIV + 1))
The maximum serial clock frequency is equal to one-fourth (0.25) the
processor’s internal peripheral clock (PCLK) frequency, which occurs when
CLKDIV is set to zero. Use the following equation to determine the value of
CLKDIV, given the PCLK frequency and desired serial clock frequency:
CLKDIV = (PCLK ÷ 4 × SCLK) – 1
If the serial clock of SPORT (SCLK) is required as general-purpose clock in
a system, only the ICLK/MSTR bit and the serial clock divider register DIVx
must be programmed.
Master Frame Sync
The bit field FSDIV specifies how many transmit or receive clock cycles are
counted before a frame sync pulse is generated. In this way, a frame sync
can initiate periodic transfers. The counting of serial clock cycles applies
to internally- or externally-generated serial clocks. The formula for the
number of cycles between frame sync pulses is:
Number of serial clocks between frame syncs = FSDIV + 1
Use the following equation to determine the value of
FSDIV, given the
serial clock frequency and desired frame sync frequency:
FSDIV = (SCLK
÷ FSCLK) – 1
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