ADSP-214xx SHARC Processor Hardware Reference 3-37
External Port
The same SDRAM with page interleaving (
SDADDRMODE bit = 1) has the fol-
lowing address map:
0x200000 logical start address int bankA
0x2000FF logical end address int bankA
0x200100 logical start address int bankB
0x2001FF logical end address int bankB
0x200200 logical start address int bankC
0x2002FF logical end address int bankC
0x200300 logical start address int bankD
0x2003FF logical end address int bankD
Timing Parameters
The controller requires many timing settings in order to correctly access
the SDRAM devices. Those that are user configurable can be found in
“SDRAM Registers” on page A-51.
Fixed Timing Parameters
The timing specifications below are fixed by the controller.
•t
MRD
(mode register delay). Required delay time to complete the
mode register write. This parameter is fixed to 2 cycles.
•t
RRD
(row active A to row active B delay). Required delay between
two different SDRAM banks. This parameter is fixed to t
RCD
+1
cycle.
•t
RC
(row access cycle). Required delay time to open and close a sin-
gle row. This parameter is fixed to t
RC
=t
RAS
+ t
RP
cycles.
•t
RFC
(row refresh cycle). Required delay time to refresh a single
row. This parameter is fixed to t
RFC
=t
RC
cycles.
•t
XSR
(exit self-refresh mode). Required delay to exit the self-refresh
mode. This parameter is fixed to t
XSR
= t
RC
cycles.
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