External Port DMA
3-102 ADSP-214xx SHARC Processor Hardware Reference
Operating Modes
This section highlights the different DMA modes which can be used with
the external port.
Internal DMA Addressing
Besides the traditional internal to external addressing type, the DMA
module also supports internal to internal transfers. This is accomplished
by indexing all external parameter registers with internal addresses. The
DMA controller recognizes the transfer by addresses and not by an addi-
tional control bit setting.
Note that the DMA channel priority changes if using internal vs.
external index addresses.
The SHARC supports another internal to internal DMA module (MTM)
which has higher priority by default but does only support standard DMA
mode. For more information, see Chapter 5, “Memory-to-Memory Port
DMA”.
TCEPx Tap Count Holds the length of the tap list (the number of taps for
delay line DMA, scatter/gather DMA).
TPEPx Tap List Pointer Holds address of an array in internal memory which
holds offsets to be used when accessing delay line DMA
in external memory. The offset represents the first
address of each read block. Applies to delay line DMA,
scatter/gather DMA
Table 3-25. Enhanced DMA Parameter Registers (Cont’d)
Register Description Comment
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