Pin Descriptions
23-2 ADSP-214xx SHARC Processor Hardware Reference
• Two pin multiplexing groups: core flag pins and external port pins.
• DAI/DPI units work together with multiplexing logic provides sys-
tem design flexibility.
Pin Descriptions
Refer to the appropriate product data sheet for pin information, including
package pinouts for the currently available package options.
Register Overview
The following registers are used for processor reset, booting, and pin
multiplexing.
Software Reset Control Register (SYSCTL). Controls the software reset
mechanism.
Running Reset Control Register (RUNRSTCTL). Controls the function-
ality of the RESETOUT pin as running reset input.
EP Control Register (EPCTL). Controls the memory chip selects for
AMI on the external port memory space during boot.
EP DMA control register (DMACx). Controls the receive configuration
for external boot DMA.
AMI Control Register (AMICTL1). Controls the AMI port configuration
for external port boot mode.
Link Port Control Register 0 (LCTL0). Controls the receive DMA for
linkport mode during boot.
SPI Control Register (SPICTL). Controls the configuration for SPI as
master or slave during SPI boot.
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