ADSP-214xx SHARC Processor Hardware Reference 3-35
External Port
Multibank Access
The processors are capable of supporting multibank operation, thus taking
advantage of the SDRAM architecture.
Operation using single versus multibank accesses depends only on
the address to be posted to the device, it is NOT an operation
mode.
Any first access to SDRAM bank (A) forces an activate command before a
read or write command. However, if any new access falls into the address
space of the other banks (B, C, or D) the SDC leaves bank (A) open and
activates any of the other banks (B, C, or D). Bank (A) to bank (B) active
time is controlled by t
RRD
= t
RCD
+ 1. This scenario is repeated until all
four banks (A–D) are opened and results in an effective page size of up to
four pages. This is because the absence of latency allows switching
between these open pages (as compared to one page in only one bank at a
time). Any access to any closed page in any opened bank (A–D) forces a
precharge command only to that bank. If, for example, two external port
DMA channels are pointing to the same internal SDRAM bank, this
always forces precharge and activation cycles to switch between the differ-
ent pages. However, if the two external port DMA channels are pointing
to different internal SDRAM banks, there is no additional overhead. See
Figure 3-8.
Furthermore the SDC supports four external memory selects containing
each SDRAM. All external banks (
MS3-0) provide multibank support, so
the maximum number of open pages is 4 × 4 = 16 pages.
Multibank access reduces precharge and activation cycles by map-
ping opcode/data among different internal SDRAM banks driven
by the A18–17 pins and external memory selects (MSx).
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