ADSP-214xx SHARC Processor Hardware Reference B-3
Peripheral Interrupt Control
performs program execution and then exits the routine by executing the
RTI (return from interrupt) instruction. However this rule does not apply
for all cases as is discussed below.
There are three interrupt acknowledge mechanisms used in an ISR
routine:
• RTI instruction
• Read-only-to-Clear (ROC) status bit + RTI instruction
• Write-1-to clear (W1C) status bit + RTI instruction
The DAI/DPI interrupt controller is designed such that in order to termi-
nate correctly, the latch register must be read to identify the source. Note
this read does automatically acknowledge the request before exiting an
interrupt routine. For the W1C mechanism, programs must write into the
specific bit of the latch register in order to terminate the interrupt
properly.
If the acknowledge mechanism rules are not followed correctly,
unwanted and sporadic interrupts will occur.
Interrupt Completion
On SHARC processors, interrupts are generated after internal transfer
completion (when the DMA count register has expired). However, in some
cases the transfer may not have terminated (due to different channel prior-
ities) and valid data still resides in the peripheral’s buffer, waiting to be
transmitted. To overcome this problem, the interrupt access completion
mode is introduced. In this mode the interrupt is generated when the last
data has left the buffer. Table B-1 provides an overview, for details refer to
the specific peripheral’s chapter.
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