Programming Model
21-22 ADSP-214xx SHARC Processor Hardware Reference
3. Program the
TWIFIFOCTL register. Indicate if transmit FIFO buffer
interrupts should occur with each byte transmitted (8 bits) or with
each 2 bytes transmitted (16 bits).
4. Program the TWIIMASK register. Enable the bits associated with the
desired interrupt sources. For example, programming the value
0x0030 results in an interrupt output to the processor when the
master transfer completes, or if a master transfer error has occurred.
5. Program the TWIMCTL register. This prepares and enables master
mode operation. As an example, programming the value 0x0201
enables master mode operation, generates a 7-bit address, sets the
direction to master-transmit, uses standard mode timing, and
transmits 8 data bytes before generating a stop condition.
Table 21-6 shows what the interaction between the TWI controller and
the processor might look like using this example.
Master Mode Receive
Follow these programming steps for a single master mode transmit:
1. Program the
TWIMADDR register. This defines the address transmit-
ted during the address phase of the transfer.
Table 21-6. Master Mode Transmit Setup Interaction
TWI Controller Master Processor
Interrupt: TWITXINT – Transmit buffer has 1 or
2 bytes empty (according to XMTINTLEN).
Write transmit FIFO buffer.
Change on the next sides always.
Interrupt Acknowledge: W1C the TWI-
IRPTL register.
... ...
Interrupt: TWIMCOMP – Master transfer com-
plete.
Change on the next sides always.
Interrupt Acknowledge: W1C the TWI-
IRPTL register
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