ADSP-214xx SHARC Processor Hardware Reference 21-23
Two Wire Interface Controller
2. Program the
TWIFIFOCTL register. Indicate if receive FIFO buffer
interrupts should occur with each byte received (8 bits) or with
each 2 bytes received (16 bits).
3. Program the TWIIMASK register. Enable bits associated with the
desired interrupt sources. For example, programming the value
0x0030 results in an interrupt output to the processor in the event
that the master transfer completes, and the master transfer has an
error.
4. Program the TWIMCTL register. Ultimately this prepares and enables
master mode operation. As an example, programming the value
0x0201 enables master mode operation, generates a 7-bit address,
sets the direction to master-receive, uses standard mode timing,
and receives 8 data bytes before generating a stop condition.
Table 21-7 shows what the interaction between the TWI controller and
the processor might look like using this example.
Table 21-7. Master Mode Receive Setup Interaction
TWI Controller Master Processor
Interrupt: TWIRXINT – Receive buffer has 1
or 2 bytes (according to RCVINTLEN).
Read receive FIFO buffer.
Change on the next sides always.
Interrupt Acknowledge: W1C the TWIIRPTL
register.
... ...
Interrupt: TWIMCOMP – Master transfer
complete.
Read receive FIFO buffer. Change on the next
sides always.
Interrupt Acknowledge: W1C the TWIIRPTL
register.
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