Programming Model
11-28 ADSP-214xx SHARC Processor Hardware Reference
5. Set the desired values for the N_SET variable using the
IDP_NSET
bits in the IDP_CTL0 register.
6. Set the IDP_FIFO_GTN_INT bit (bit 8 of the DAI_IMASK_RE register)
to HIGH and set the corresponding bit in the DAI_IMASK_FE regis-
ter to LOW to unmask the interrupt. Set bit 8 of the
DAI_IMASK_PRI register (IDP_FIFO_GTN_INT) as needed to generate a
high priority or low priority core interrupt when the number of
words in the FIFO is greater than the value of N set.
7. Enable the PDAP by setting IDP_PDAP_EN (bit 31 in the IDP_PP_CTL
register), if required.
8. Enable the IDP by setting the IDP_EN bit (bit 7 in the IDP_CTL0
register) and the IDP_ENx bits in the IDP_CTL1 register.
In older SHARC processors, the IDP starts shifting data before the
IDP is enabled. However, the shifted data is latched at the next
frame sync edge only if the IDP is enabled. Therefore, whether the
first channel received by the IDP is left/right depends on the
instant when the IDP is enabled— which may lead to channel
swapping.
Additional Notes
When IDPs are used to receive data from external devices, there is a
sequence to be followed to enable the IDP ports when configured to
receive data in I
2
S mode. Failing to follow this sequence can give rise to
channel shift or swap.
1. Connect the frame sync internally using the SRU (Signal Routing
Unit) to the DAI interrupt.
2. Configure the DAI interrupt (MISCA) for the inactive edge of the
frame sync.
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