Interrupts
9-36 ADSP-214xx SHARC Processor Hardware Reference
There are two signal naming conventions: the DPI interrupt con-
troller bits are named DPI_13-5_INT and its corresponding SRU
signals are named MISCB8-0_I.
Signals from the SRU2 group C can be used to generate interrupts. For
example, when DPI_13_INT (bit 13) of DPI_IMASK is set to one, any signals
from the miscellaneous channel 8 MISCB8_I generates an interrupt. If set
to one, the DPI triggers an interrupt in the core and the interrupt latch is
set. A read of this bit does not reset it to zero. The bit is only set to zero
when the cause of the interrupt is cleared. A DPI interrupt indicates the
source (in this case, miscellaneous, Channel 8), and checks the IVT for an
instruction (next operation) to perform.
Table 9-7 provides an overview of DPI miscellaneous interrupts.
DAI/DPI Interrupt Mask Events
For interrupt sources that correspond to waveforms (as opposed to DAI
event signals such as DMA complete or buffer full), the edge of a wave-
form may be used as an interrupt source as well. Just as interrupts can be
generated by a source, interrupts can also be generated and latched on the
rising (or falling) edges of a signal.
Only the DAI interrupt controller latches interrupts on both edges.
This ability does not exist in the core interrupt controller.
When a signal comes in, the system needs to determine what kind of sig-
nal it is and what kind of protocol, as a result, to service. The preamble
Table 9-7. DPI Miscellaneous Interrupt Overview
Interrupt
Source
Interrupt Condition Interrupt
Completion
Interrupt
Acknowledge
Default IVT
DPI MISCB
(9 channels)
– Rising edge
– Falling edge
– Rising/falling edge
Read-to-clear
DPI_IRPTL_x
+ RTI instruction
P14I
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