Functional Description
21-6 ADSP-214xx SHARC Processor Hardware Reference
FIFO Control Register (TWIFIFOCTL). The FIFO control register
affects only the FIFO and is not tied in any way with master or slave mode
operation.
FIFO Status Register (TWIFIFOSTAT). The fields in the TWI FIFO sta-
tus register indicate the state of the FIFO buffers’ receive and transmit
contents. The FIFO buffers do not discriminate between master data and
slave data. By using the status and control bits provided, the FIFO can be
managed to allow simultaneous master and slave operation.
Functional Description
Figure 21-1 illustrates the overall architecture of the TWI controller.
The peripheral interface supports the transfer of 32-bit wide data and is
used by the processor in the support of register and FIFO buffer reads and
writes.
The register block contains all control and status bits and reflects what can
be written or read as outlined by the programmer’s model. Status bits can
be updated by their respective functional blocks.
The FIFO buffer is configured as a 1-byte-wide, 2-deep transmit FIFO
buffer and a 1-byte-wide, 2-deep receive FIFO buffer.
The transmit shift register serially shifts its data out externally off chip.
The output can be controlled to generate acknowledgements or it can be
manually overwritten.
The receive shift register receives its data serially from off chip. The
receive shift register is 1 byte wide and data received can either be trans-
ferred to the FIFO buffer or used in an address comparison.
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