ADSP-214xx SHARC Processor Hardware Reference 7-27
Pulse Width Modulation
Debug Features
The module contains four debug status registers (PWMDBG3–0), which can
be used for debug aid. Each register is available per unit. The registers
return current status information about the AH, AL, BH, BL output pins.
Status Debug Register
The module contains four debug status registers (PWMDBG3–0), which can
be used for debug aid. Each register is available per unit. The registers
return current status information about the AH, AL, BH, BL output pins.
Emulation Considerations
An emulation halt does not stop the PWM period counter.
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
PWM Effect Latency
After the PWM registers are configured the effect latency is 1 PCLK cycle
minimum and 2
PCLK cycles maximum.
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