DDR2 DRAM Controller (ADSP-2146x)
3-62 ADSP-214xx SHARC Processor Hardware Reference
bits in the
DDR2CTL0 register. The bank address width is three bits as
shown in Table 3-11.
Row Address Width (DDR2RAW). These bits in the DDRCTL0 register
determine the row width of the DDR. The DDR2RAW bits can be pro-
grammed for row widths of 8 to 15.
Column Address Width (DDR2CAW). The DDR2 memory control reg-
ister also includes external bank specific programmable parameters. The
external bank can be configured for a different DDR2 size. The DDR
controller determines the internal DDR2 page size from the X16DE and
DDR2CAW parameters. Page sizes of 256, 512, 1K, 2K and 4K words are
supported.
The mapping of the addresses depends on the row address width
(DDR2RAW), column address width (DDR2CAW), and the address mode
bit (DDR2ADDRMODE) setting.
16-Bit Address Mapping
Even if the external data width is 16 bits, the processor supports only
32-bit data accesses. The DDR2 controller performs two 16-bit accesses to
get and place 32-bit data. The controller takes the IA address and appends
one extra bit to the LSB to generate the address externally.
Table 3-11. External Memory Address Bank Decoding
IA[27] IA[26] External Bank
00Bank 0
01Bank 1
10Bank 2
11Bank 3
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