ADSP-214xx SHARC Processor Hardware Reference 4-21
Link Ports—ADSP-2146x
LSRs are gated by mask bits and then ORed together to generate the link
service request interrupt. The
LSRQ interrupt requests may be masked by
the receive (LRRQ_MSK) or transmit (LTRQ_MSK) bits of the LCTLx register.
When the mask bit is set, the interrupt is allowed to pass into the inter-
rupt priority encoder. The maximum latency between asserting the LCLK
or LACK signals and latching an interrupt is 2 to 3 PCLK cycles.
The interrupt routine must read the LSTATx register to determine which
link port to service and whether it is a transmit or receive request. The
link service request status of the port is set whenever the port is not enable
and one of LxACK or LxCLK is asserted high.
If link service requests are in use, they should be masked out when the
assigned link buffers are being enabled, disabled, or when the link port is
being unassigned in LCTLx register. Otherwise, spurious service requests
may be generated.
To avoid the possibility of spurious interrupts, programs can mask
the LSRQ interrupts and poll the appropriate request status bits
until it is cleared and then unmask the interrupt.
Debug Features
The following sections provide information on features that help in
debugging link port software.
Shadow Register
The shadow status register can be read without clearing the interrupt bits.
For more information, see “Link Port Registers” on page A-63.
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