Peripheral Registers
A-116 ADSP-214xx SHARC Processor Hardware Reference
updated when the WDT is disabled and WDT configuration space is
unlocked by programming the command in the
WDTUNLOCK register.
Clock Select (WDTCLKSEL)
This register, described in Table A-74, can only be updated when the
WDT is disabled and WDT configuration space is unlocked by program-
ming the command in the WDTUNLOCK register. Writes to the WDTCLKSEL
register are ignored after the WDT is enabled.
Note: This register is reset on external hardware reset only. This ensures
that the selected clock source remains the same even after a WDT gener-
ated reset is asserted.
Table A-73. WDTTRIP Register Bit Descriptions (RW)
Bit Name Description
3–0 TRIPVAL Current Value of Trip Counter. This is the trip counter
value, programmable from 0 to 15. The number of times
WDT can expire is programmable by the TRIPVAL field
Reading this register also gives the current value of the trip
counter.
7–4 (RO) CURTRIPVAL Current Number of WDT Resets. Reports all current WDT
generated resets (
WDTRSTO asserted).
Table A-74. WDTCLKSEL Register Bit Descriptions (RW)
Bit Name Description
0CLKSEL Clock Select. When this bit = 0, the WDTCLK source can
be an external clock applied to the WDT_CLKIN pin or an
external ceramic Oscillator connected to the WDT_CLKIN
and WDT_CLKO pins.
0 = Selects ceramic oscillator output or external clock
1 = Selects internal RC oscillator output
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