Peripherals Routed Through the DAI
A-174 ADSP-214xx SHARC Processor Hardware Reference
SPORT Error Status Register (SPERRSTAT)
The
SPERRSTAT register checks the status of SPORT interrupts (see
Figure A-92).
Input Data Port Registers
The input data port (IDP) provides an additional input path to the pro-
cessor core. The IDP can be configured as 8 channels of serial data or 7
channels of serial data and a single channel of up to a 20-bit wide parallel
data.
Input Data Port DMA Control Registers
For information on these registers, see “Standard DMA Parameter Regis-
ters” on page 2-4.
Figure A-92. SPERRSTATx Register (RO)
SP5 DERRB
SP7 DERRB
SP4 FSERR
SP2 FSERR
SP1 FSERR
SP0 FSERR
SP7 DERRA
SP6 DERRB
SP6 DERRA
SP0 DERRA
SP0 DERRB
SP1 DERRA
SP1 DERRB
SP2 DERRA
SP2 DERRB
SP5 DERRA
SP4 DERRB
SP4 DERRA
SP3 DERRA
SP3 DERRB
SP5 FSERR
SP6 FSERR
SP7 FSERR
SP3 FSERR
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
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