ADSP-214xx SHARC Processor Hardware Reference A-199
Registers Reference
Sony/Philips Digital Interface Registers
The following sections describe the registers that are used to configure,
enable, and report status information for the S/PDIF transceiver.
Transmitter Registers
The following sections describe the S/PDIF transmitter registers.
Transmit Control Register (DITCTL)
This 32-bit register’s bits are shown in Figure A-107 and described in
Table A-104.
17 CLKD_SYNC Enable Synchronization of Clock D With External Frame
Sync.
0 = Clock disabled
1 = Clock enabled
18 CLKD_SOURCE_IOP Enable Clock D Input Source.
0 = Output selected by CLKDSOURCE bit
1 = PCLK selected for clock D
19 FSD_SOURCE_IOP Enable Frame Sync D Input Source.
0 = Output selected by FSDSOURCE bit
1 = PCLK selected for frame sync D
Table A-103. PCG_SYNC2 Register Bit Descriptions (RW) (Cont’d)
Bit Name Description
To Next Page
Loading...
Need help?
General
