ADSP-214xx SHARC Processor Hardware Reference 13-13
Sony/Philips Digital Interface
In SCDF mode, the transmitter sends successive audio samples of the
same signal across both sub frames, instead of channel A and B. The trans-
mitter will transmit at half the sample rate of the input bit stream. The
DIT_SCDF bit (bit 4 in the DITCTL register selects SCDF mode. When in
SCDF mode, the DIT_SCDF_LR bit (bit 5 in the DITCTL register) register
decides whether left or right channel data is transmitted.
S/PDIF Receiver
The S/PDIF receiver (Figure 13-8) is compliant with all common serial
digital audio interface standards including IEC-60958, IEC-61937,
AES3, and AES11. These standards define a group of protocols that are
commonly associated with the S/PDIF interface standard defined by
AES3, which was developed and is maintained by the Audio Engineering
Society. The AES3 standard effectively defines the data and status bit
structure of an S/PDIF stream. AES3-compliant data is sometimes
referred to as AES/EBU compliant. This term highlights the adoption of
the AES3 standard by the European Broadcasting Union.
Functional Description
The S/PDIF receiver is enabled at default to receive in two-channel
mode. If the receiver is not used, programs should disable the
receiver as the digital PLL may produce unwanted switching noise.
If the receiver is not used, programs should disable the digital PLL to
avoid unnecessary switching. This is accomplished by writing into the
DIR_RESET bit in the DIRCTL register. In most cases, when the S/PDIF
receiver is used, this register does not need to be changed. After the SRU
programming is complete, write to the
DIRCTL register with control values.
At this point, the receiver attempts to lock.
For a detailed description of this register, see “Receive Control Register
(DIRCTL)” on page A-204.
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