Effect Latency
11-26 ADSP-214xx SHARC Processor Hardware Reference
Core FIFO Write
The core may also write to the FIFO. When it does, the audio data word is
pushed into the input side of the FIFO (as if it had come from the SRU
on the channel encoded in the three LSBs). This can be useful for verify-
ing the operation of the FIFO, the DMA channels, and the status portions
of the IDP. The IDP_STAT1 register returns the current state of the
read/write index pointers from FIFO.
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
IDP Effect Latency
The IDP is ready to start receiving data one serial clock cycle (SCLK) after
it is enabled by setting IDP_EN bit. No LRCLK edges are lost from this point
on.
Disabling IDP DMA by resetting the
IDP_DMA_EN bit requires 1 PCLK
cycle. Disabling an individual DMA channel by resetting the IDP_DMA_ENx
bit requires 2
PCLK cycles.
Programming Model
The following sections provide procedures that are helpful when program-
ming the input data port.
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