Programming Model
10-58 ADSP-214xx SHARC Processor Hardware Reference
become non-empty by polling the
DXS0_A/B bits. For core mode
operation, initialize the transmit buffer with the first data word to
be transmitted.
7. Configure and enable multichannel in the multichannel control
registers (SPMCTLx and SPMCTLy).
Multichannel Mode Backward Compatibility
In previous SHARC models, the serial port pair used the same control reg-
ister (SPMCTL01) to program multichannel mode. In the ADSP-214xx
processors, this register is simply renamed to SPMCTL0 and a new register,
SPMCTL1 has been added. Note that both however are identical. Programs
using the older code simply need to change from the SPMCTL01 register to
the SPMCTL0 register or the SPMCTL1 register.
The following steps should be taken to port the code to the ADSP-214xx
products.
1. Instead of programming SPMCTLxy only, program both SPMCTLx and
SPMCTLy.
2. In previous processors the data direction bit in the SPCTL register
was hard coded in multichannel mode (where the even port is
always the transmitter and the odd port is always the receiver). But
in the ADSP-214xx processors, the direction (
SPTRAN bit) is hon-
ored and therefore should be set as required.
3. Routing models for hard coded multichannel pairs used the even
SPORT for the clock and the odd SPORT for the frame sync. The
TDV signal was derived from the even frame sync. In the
ADSP-214xx processors, these limitations no longer apply. All
SPORTs operate completely independently. Therefore every
SPORT requires the clock and frame sync to be routed. The TDV
signal is separate and is fed into the SRU unit.
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