Programming Model
11-30 ADSP-214xx SHARC Processor Hardware Reference
• The global
IDP_EN bit (bit 7 in the IDP_CTL0 register).
Starting a Ping-Pong DMA Transfer
To start a ping-pong DMA transfer from the FIFO to memory:
1. Clear the FIFO by setting (= 1) the
IDP_FFCLR bit (bit 31 in the
IDP_CTL1 register).
2. While the global IDP_DMA_EN and IDP_EN bits are cleared (=0), set
the values for the following DMA parameter registers that corre-
spond to channels 7–0.
3. Keep the clock and the frame sync input of the serial inputs and/or
the PDAP connected to LOW, by setting proper values in the SRU
registers.
4. Refer to “Setting Miscellaneous Bits” above.
5. Connect all of the required inputs to the IDP by writing to the
SRU registers.
6. Enable the channel’s IDP_ENx, IDP_DMA_ENx and IDP_PINGx bit
settings.
7. Start DMA by setting:
• The
IDP_PDAP_EN bit (bit 31 in IDP_PP_CTL register if the
PDAP is required).
• The global
IDP_DMA_EN bit of the IDP_CTL0 register to enable
the standard DMA of the selected channel.
• The global
IDP_EN bit (bit 7 in the IDP_CTL0 register).
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